As the capacity of semiconductor memory devices increases, the sizes of chips on which the devices are formed also becomes larger to accommodate the larger devices. In addition, as the sizes of the chips increases, the length of data lines or data paths for transferring data therein also typically becomes larger. Such increases in data line and data path length may result in increased wiring resistance and reduce the maximum frequency at which memory devices may reliably operate.
Techniques to improve operating speed include wave pipelining techniques. An exemplary wave pipelining technique is disclosed in article by D. Wong et al., entitled "WP3.6: A Bipolar Population Counter Using Wave-Pipelining to Achieve 2.5.times. Normal Clock Frequency", IEEE International Solid-State Circuit Conference (ISSCC) Digest of Technical Papers, pp. 56-57, February (1992). Another wave pipelining technique is disclosed in U.S. Pat. No. 5,703,815 to Kuhara et al. entitled "High-Speed Semiconductor Memory System". In particular, the Kuhara et al. patent discloses a technique to enhance the wave-pipeline operational frequency of a memory system by reducing cycle time. The cycle time is reduced by reducing a difference in the signal delay time caused by differences in data path lengths. According to Kuhara et al., the difference in signal delay time can be reduced by inserting a delay circuit into a signal path having a smaller delay time between an address input section and a data output section. A wave pipelining technique is also disclosed in an article by Hoi-Jun Yoo et al., entitled "A 150 MHz 8-Banks 256M Synchronous DRAM with Wave Pipelining Methods", IEEE International Solid-State Circuit Conference Digest of Technical Papers, paper FA 14.4, pp. 250-251 (1995).
Referring now to FIGS. 1-4, an integrated circuit memory device that utilizes wave pipelining is disclosed. In particular, FIG. 1 illustrates a memory device 1 (e.g., DRAM device) having a memory cell array 10 therein. A row decoder circuit 14 is electrically coupled to the memory cell array 10 by a plurality of word lines WL0-WLm. The row decoder circuit 14 receives row addresses RAi from an address buffer circuit 12. The address buffer circuit 12 receives an external address XAi and is responsive to a read command RMD and an internal clock signal PCLK. The internal clock signal PCLK is generated by a clock buffer circuit 22 that is responsive to an external clock signal XCLK. The address buffer circuit 12 also generates column addresses CAi and a bank select signal CAi.sub.-- BANK. The column addresses CAi are provided to a column decoder circuit 16. The column decoder circuit 16 generates column select signals CSLi and is responsive to a column select enable signal CSLE and a column select disable signal CSLD. The column select enable signal CSLE and the column select disable signal CSLD are generated by a CSL control circuit 15. This CSL control circuit 15 is responsive to the internal clock signal PCLK, the bank select signal CAi.sub.-- BANK and a delayed version of the internal clock signal PCLKD.
The column select signals CSLi are provided to a column pass gate circuit 20, as illustrated. The column pass gate circuit 20 is electrically coupled to the memory cell array 10 by a bit line sense amplifier circuit 18. As will be understood by those skilled in the art, the bit line sense amplifier circuit 18 senses and amplifies data signals that are generated on a plurality of bit lines BL0-BLn during reading operations. The column pass gate circuit 20 also passes "read" data to a data line sense amplifier circuit 24. The data line sense amplifier circuit 24 passes the "read" data to an output register 26 in response to an I/O control signal PIOSi.
The memory device 1 of FIG. 1 supports burst mode operation. Accordingly, the column address signals CAi that are applied to the column decoder circuit 16 can serve as initial column addresses. Although not shown, a burst counter and a burst address generator can be used to generate a plurality of consecutive column addresses (i.e., burst column addresses) in response to the initial column address. The number of consecutive burst column addresses that are generated is typically a function of a preselected burst length (BL). These burst column addresses are then decoded in order by the column decoder circuit 16 as respective column select signals CSLi.
Referring still to FIG. 1, the output register 26 latches data (e.g., read data) provided by the data line sense amplifier circuit 24, and is responsive to register input control signals DLLi and register output control signals CDQi. The register input control signals DLLi are generated in sequence by a register input control circuit 28. The register input control circuit 28, which is illustrated in detail by FIG. 3, is responsive to the bank select signal CAi.sub.-- BANK and the delayed internal clock signal PCLKD. The register output control signals CDQi are generated by a register output control circuit 30. The register output control circuit 30 is responsive to the delayed internal clock signal PCLKD, the read command RMD and signal CLi. A read command generating circuit 34 generates the read command RMD in-sync with the internal clock signal PCLK and in response to a write enable signal WEB, a column address strobe signal CASB and a chip select signal CSB.
An exemplary output register 26 is illustrated by FIG. 2. This register 26 includes a plurality of latch units L1-L4. A plurality of input switches SW1-SE4 are also provided so that read data at node NDIN can be loaded into each latch unit. Latch unit L5 is provided to prevent node NDIN from floating. The switches are responsive to the register input control signals DLLi. The switches may comprise CMOS transmission gates or NMOS transistors, for example. A plurality of output switches SW5-SW8 are also provided so that data stored by latch units L1-L4 can be passed sequentially to a data output buffer 32 that is responsive to signal PCLKDQ. As will be understood by those skilled into the art, a plurality of bits of serial data (e.g., 4 bits) may be provided by the data line sense amplifier circuit 24 and these serial data bits may be loaded in sequence into each of the parallel latch units L1-L4 by sequencing signals DLL0-DLL3 through the following pattern: 1000, 0100, 0010, 0001. A similar pattern for the output signals CDQ1-CDQ4 may also be used to pass the latched data in a serial fashion to the output buffer 32.
Referring now to FIG. 3, a conventional register input control circuit 28 is illustrated. This control circuit 28 is responsive to the delayed clock signal PCLKD and the bank select signal CAi.sub.-- BANK. In particular, both the delayed clock signal PCLKD and bank select signal CAi.sub.-- BANK are provided as inputs to a two-input NAND gate 51. The output of the NAND gate 51 is provided to a delay circuit comprising an even number of inverters (e.g., inverter 52 at the input and inverter 53 at the output). As will be understood by those skilled in the art, the signal at the output of inverter 54 at node NA will represent a delayed version of the delayed clock signal PCLKD once the bank select signal CAi.sub.-- BANK has been set to a logic 1 level. Thus, the signal at node NA (input to inverter 55) will be in-sync with the delayed clock signal PCLKD and each 0.fwdarw.1 transition of the delayed clock signal PCLKD will translate into a 0.fwdarw.1 transition at node NA and a 1.fwdarw.0 transition at node NB (the output of inverter 55). Moreover, after the outputs DLL0-DLL3 of the register input control circuit 28 have been reset to the state "1000" by driving the reset signal RESET to a logic 1 level, each 0.fwdarw.1 transition at node NA will cause the state of the outputs DLL0-DLL3 to transition one step in the cyclical sequence 1000.fwdarw.0100.fwdarw.0010.fwdarw.0001.fwdarw. . . . As illustrated, a 0.fwdarw.1transition on the RESET signal line will cause the output of inverter 65 to transition to a logic 0 level. When this occurs, PMOS pull-up transistors. 72, 81 and 90 will turn on and drive outputs DLL1, DLL2 and DLL3 to logic 0 levels. NMOS pull-down transistor 64 will also turn on and drive output DLL0 to a logic 1 level.
FIG. 4 is a timing diagram that illustrates operation of the memory device of FIGS. 1-3. In particular, FIG. 4 is a timing diagram that illustrates a burst read operation using a conventional wave pipeline method. The timing diagram corresponds to a device having a CASB latency of 2 and a burst length of 4. As illustrated, each leading edge of an external clock signal XCLK triggers a pulse of an internal clock signal PCLK having the same period. The delay circuit 23 also generates the delayed clock signal PCLKD as a delayed version of the internal clock signal PCLK. Thus, each pulse of the delayed clock signal PCLKD is in-sync with a respective pulse of the internal clock signal PCLK. The column select enable signal CSLE and the column select disable signal CSLD are also generated in-sync with the internal clock signal PCLK. A rising edge of the column select enable signal CSLE results in a rising 0.fwdarw.1 transition of the column select signal CSLi and a rising edge of the column select disable signal CSLD results in a falling 1.fwdarw.0 transition of the column select signal CSLi. As will be understood by those skilled in the art, a rising edge of the column select signal CSLi initiates a transfer of read data out of the memory cell array 10 during a reading operation. This read data is passed through the bit line sense amplifier circuit 18, the column pass gate circuit 20 and the data line sense amplifier circuit 24, to node NDIN of the output register 26. In particular, the delays associated with the read data path may be such that node NDIN receives the first bit of read data D0 at the commencement of clock interval C1 (i.e., after a time interval of Tb, as measured from a rising edge of the external clock signal XCLK), as illustrated by FIG. 4. The output signals DLL0-DLL3 from the register input control circuit 28 are also set to transition at time points that are intermediate the first, second, third and fourth clock intervals C1-C4. For example, the transition of output signal DLL0 from 1.fwdarw.0 during the first clock cycle C1 is in-sync with a transition of PCLK and PCLKD during the zeroth clock cycle C0. As illustrated, the transition of output DLL0 from 1.fwdarw.0 takes place after a time interval Ta, as measured from a rising edge of the external clock signal XCLK.
Accordingly, the time interval Tc represents the period of time during which read data at node NDIN can be successfully latched into the register (e.g., latch L1). This period of time is typically referred to as the "data latch margin". Data that has been successfully latched may then be passed to the output buffer in-sync with the register output control signals CDQi. Unfortunately, because the time interval Tb may be influenced significantly by changes to the parameters associated with the memory cell array 10, and because the fabrication design rules associated with the memory array and closely related circuits are typically much more stringent than the design rules associated with other peripheral circuits (e.g., delay circuit 23, register input control circuit 28 and register 26, for example), relatively slight variations in process conditions during fabrication may cause the time interval Tb to increase in duration without a concomitant increase in the duration of time interval Ta. For example, variations in process conditions may cause the data D0 to become valid after time interval Tb' instead of time interval Tb. In such cases, the data latch margin may decrease to value equal to Tc'. If the value of Tc' decreases to zero or becomes negative, data read failures likely will occur. To correct such failures, the operating speed of a DRAM device having a multi-stage pipeline may be reduced. Unfortunately, the operating speed of DRAM devices having a single-stage pipeline typically cannot be reduced to correct such failures.
Thus, notwithstanding the above-described memory devices, there continues to be a need for memory devices that have higher operating reliability and are less susceptible to failure in response to process variations that occur during fabrication.